IIT-Hyderabad develops ‘pendant’ that can monitor heart rhythm

"There are several wearable devices that can keep track of the heart rhythm. But they are all connected to a central server to which the ECG signals are transmitted and later interpreted by a professional," Acharyya said. "Our chip does all of this, yet consuming as little as one milliwatt battery power," he added. "When compared to a chip that can store five hours of data, our chip can save 35 hours of data in a compressed format," said Acharyya

RF choke based methodology for flange effect mitigation and antenna isolation improvement in bistatic radars of aerospace vehicles

This paper presents a novel technique for mitigation of flange effect and antenna transmit to receive isolation improvement methodology using RF choke for the bistatic radars of aerospace vehicles. The presence of flange causes variation in antenna radiation pattern, by an increase in sidelobe level, decrease in gain and dip in roll pattern, thereby degradation in the performance of the antenna. An RF choke adjacent to the waveguide wall is introduced to nullify the undesirable effects of the flange. This Paper demonstrates through simulation and experimentation that this choke effectively suppresses the surface wave and can be applied in many types of antennas to improve the radiation pattern deteriorated by parasitic elements. It is also demonstrated through measurements that the isolation from transmit to receive antenna is improved by introducing choke, with this technique antenna isolation is enhanced by 23 dB with 11 dB antenna gain. The gain and sidelobe improvement of the antenna with RF choke is 2 dB, and 6 dB, respectively. The proposed array antenna is fabricated with and without choke, measurements are performed and test results are presented. The isolation test between transmit & receive antenna is performed in an anechoic chamber and test results are presented

A Low Complexity Architecture for Online On-chip Detection and Identification of f-QRS Feature for Remote Personalized Health Care Applications

This paper introduces a novel low complexity highly accurate on-chip architecture for the detection of fragmented QRS (f-QRS) feature including notches and local extrema in the QRS complexes and subsequently identifies its various morphologies (Notched S, rsR', RsR' without elevation etc.) under the real-time environment targeting remote personalized health care. The proposed architecture uses the outcome of recently proposed Hybrid feature extraction algorithm (HFEA) [1] Level 3 detailed coefficients and detects and identifies the fragmentation feature from the QRS complex based on the criteria of the positions, and the magnitudes of the extrema (maxima and minima) and notches from the wavelet coefficients with no extra cost in terms of arithmetic complexity. To verify the proposed architecture 100 patients were randomly selected from the MIT-BIH Physio Net PTB database and their ECG was examined by two experienced cardiologists individually and the results were compared with those obtained from the architecture output wherein we have achieved 95 % diagnostic matching

IIT-Hyderabad device can scan ECG for heart disease

Researchers from IIT-Hyderabad have designed a device to diagnose medical conditions from real-time ECG dat

IIT-H develops low power chip for AI-enabled devices

With the advent of artificial intelligence devices in day to day life, researchers at the Indian Institute of Technology, Hyderabad (IIT-H) have developed low power chips that can perform high level computation with constraint power consumption

IIT Hyderabad team develops low power chips for Artificial Intelligence devices

Indian Institute of Technology, Hyderabad researchers have developed low power chips that can be used in Artificial Intelligence-powered devices. They have developed magnetic quantum-dot cellular automata (MQCA) based nanomagnetic logic architectural design methodology of approximate arithmetic circuit

Personalized reduced 3-lead system formation methodology for Remote Health Monitoring applications and reconstruction of standard 12-lead system

Remote Health Monitoring (RHM) applications encounter limitations from technological front viz. bandwidth, storage and transmission time and the medical science front i.e. usage of 2-3 lead systems instead of the standard 12-lead (S12) system. Technological limitations constraint the number of leads to 2-3 while cardiologists accustomed with 12-Lead ECG may find these 2-3 lead systems insufficient for diagnosis. Thus, the aforementioned limitations pose self-contradicting challenges for RHM. A personalized reduced 2/3 lead system is required which can offer equivalent information as contained in S12 system, so as to accurately reconstruct S12 system from reduced lead system for diagnosis. In this paper, we propose a personalized reduced 3-lead (R3L) system formation methodology which employs principal component analysis, thereby, reducing redundancy and increasing SNR ratio, hence, making it suitable for wireless transmission. Accurate S12 system is made available using personalized lead reconstruction methodology, thus addressing medical constraints. Mean R2 statistics values obtained for reconstruction of S12 system from the proposed R3L system using PhysioNet's PTB and TWA databases were 95.63% and 96.37% respectively. To substantiate the superior diagnostic quality of reconstructed leads, root mean square error (RMSE) metrics obtained upon comparing the ECG features extracted from the original and reconstructed leads, using our recently proposed Time Domain Morphology and Gradient (TDMG) algorithm, have been analyzed and discussed. The proposed system does not require any extra electrode or modification in placement positions and hence, can readily find application in computerized ECG machines

Fast 3D Integrated Circuit Placement Methodology using Merging Technique

In the recent years the advancement in the field of microelectronics integrated circuit (IC) design technologies proved to be a boon for design and development of various advanced systems in-terms of its reduction in form factor, low power, high speed and with increased capacity to incorporate more designs. These systems provide phenomenal advantage for armoured fighting vehicle (AFV) design to develop miniaturised low power, high performance sub-systems. One such emerging high-end technology to be used to develop systems with high capabilities for AFVs is discussed in this paper. Three dimensional IC design is one of the emerging field used to develop high density heterogeneous systems in a reduced form factor. A novel grouping based partitioning and merge based placement (GPMP) methodology for 3D ICs to reduce through silicon vias (TSVs) count and placement time is proposed. Unlike state-of-the-art techniques, the proposed methodology does not suffer from initial overlap of cells during intra-layer placement which reduces the placement time. Connectivity based grouping and partitioning ensures less number of TSVs and merge based placement further reduces intra layer wire-length. The proposed GPMP methodology has been extensively against the IBMPLACE database and performance has been compared with the latest techniques resulting in 12 per cent improvement in wire-length, 13 per cent reduction in TSV and 1.1x improvement in placement time

Secure Scan Design with a Novel Methodology of Scan Camouflaging

Scan based attacks are the major security concerns of a design. These attacks are majorly employed to understand the camouflaged logic during reverse engineering. The state-of-the-art techniques like scan chain scrambling hinder accessibility of scan chains, but are prone to layout level reverse engineering attacks. In the proposed methodology, the scan design is secured by adding an extra scan input port (DSI) to the flipflop using dummy contacts, which ensure that DSI cannot be distinguished from SI port even with layout based reverse engineering techniques. Dummy scan chain connections are introduced in the design by connecting DSI port to the nearby flipflop Q output port. Our proposed method can withstand Reset-and-scan attack, Incremental SAT-based attack and the recent ScanSAT attack. The performance of this concept is measured in terms of frequency and total power consumption on IWLS-2005 benchmark circuits having up to 1380 flipflops with 40nm technology library. The delay is effected by a maximum of 2.2% with 50% obfuscation without any impact on power, pattern generation time and scan test time